143 lines
3.4 KiB
C++
143 lines
3.4 KiB
C++
/*
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* Copyright 2023 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef C2_RK_CHIP_CAP_DEF_H_
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#define C2_RK_CHIP_CAP_DEF_H_
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#include <stdio.h>
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#include "rk_type.h"
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typedef enum _C2ChipType {
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RK_CHIP_UNKOWN = 0,
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// 2928 and 3036 no iep
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RK_CHIP_2928,
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RK_CHIP_3036,
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RK_CHIP_3066,
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RK_CHIP_3188,
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// iep
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RK_CHIP_3368H,
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RK_CHIP_3368A,
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RK_CHIP_3128H,
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RK_CHIP_3128M,
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RK_CHIP_312X,
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RK_CHIP_3326,
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// support 10bit chips
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RK_CHIP_10BIT_SUPPORT_BEGIN,
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// 3288 support max width to 3840
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RK_CHIP_3288,
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// support 4k chips
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RK_CHIP_4K_SUPPORT_BEGIN,
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RK_CHIP_322X_SUPPORT_BEGIN,
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RK_CHIP_3228A,
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RK_CHIP_3228B,
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RK_CHIP_3228H,
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RK_CHIP_3328,
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RK_CHIP_3229,
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RK_CHIP_322X_SUPPORT_END,
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RK_CHIP_3399,
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RK_CHIP_1126,
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RK_CHIP_3562,
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// support 8k chips
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RK_CHIP_8K_SUPPORT_BEGIN,
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RK_CHIP_356X,
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RK_CHIP_3528,
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RK_CHIP_3576,
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RK_CHIP_3588,
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RK_CHIP_8K_SUPPORT_END,
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RK_CHIP_10BIT_SUPPORT_END,
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RK_CHIP_3368,
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RK_CHIP_4K_SUPPORT_END,
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} C2ChipType;
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typedef enum _C2Cap10bit {
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C2_CAP_10BIT_NONE = 0, /* unsupport 10bit */
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C2_CAP_10BIT_AVC = 0x1,
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C2_CAP_10BIT_HEVC = 0x2,
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C2_CAP_10BIT_VP9 = 0x4,
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} C2Cap10bit;
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typedef enum _C2CompressMode {
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C2_COMPRESS_MODE_NONE = 0, /* no compress */
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C2_COMPRESS_AFBC_16x16 = 1,
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C2_COMPRESS_RFBC_64x4 = 2,
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C2_COMPRESS_MODE_BUTT
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} C2CompressMode;
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typedef struct {
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MppCodingType codecId;
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C2CompressMode fbcMode;
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/* output padding, for setcrop before display */
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uint32_t offsetX;
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uint32_t offsetY;
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} C2FbcCaps;
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typedef enum _C2ScaleMode {
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C2_SCALE_MODE_NONE = 0,
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C2_SCALE_MODE_META = 1, /* output scale meta to the display */
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C2_SCALE_MODE_DOWN_SCALE = 2, /* output down scale stream directly */
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} C2ScaleMode;
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typedef struct {
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const char *chipName;
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C2ChipType chipType;
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int32_t fbcCapNum;
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C2FbcCaps *fbcCaps;
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uint32_t scaleMode : 2;
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uint32_t cap10bit : 3;
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uint32_t grallocVersion : 4;
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uint32_t hdrMetaCap : 1;
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uint32_t reserved : 22;
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} C2ChipCapInfo;
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class C2RKChipCapDef {
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public:
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static C2RKChipCapDef *get() {
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static C2RKChipCapDef instance;
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return &instance;
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}
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const char* getChipName();
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C2ChipType getChipType();
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uint32_t getHdrMetaCap();
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uint32_t getScaleMode();
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uint32_t getGrallocVersion();
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uint32_t getFbcOutputMode(MppCodingType codecId);
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uint32_t getFbcMinStride(uint32_t fbcMode);
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uint32_t getFbcOutputOffset(MppCodingType codecId, uint32_t *offsetX, uint32_t *offsetY);
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bool is10bitSupport(MppCodingType codecId);
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bool hasRkVenc();
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private:
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C2RKChipCapDef();
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~C2RKChipCapDef() {};
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C2ChipCapInfo *mChipCapInfo;
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};
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#endif // C2_RK_CHIP_CAP_DEF_H_
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